Such integratable, controllable delay devices are widely used for delaying a clock signal in integrated semiconductor circuits. One particular use of the delay device is in a delay locked loop. Delay locked loops are used to produce clock signals with a predetermined phase angle in digitally processing circuits. For example, in synchronously operated integrated semiconductor memories which operate on the double data rate principle, i.e., DDR SDRAMs (Double Data Rate Synchronous Dynamic Random Access Memories), a delay locked loop (DLL) is used in order to account for internal signal delay times in production, on the output side, of a clock signal, with the data to be emitted being produced in synchronism with an input clock signal supplied at a different point in the integrated circuit.
A delay locked loop compares the clock signal which is supplied to the input side of the delay unit with the delayed clock signal that is produced on the output side, and readjusts the delay as a function of the phase difference until the phase difference is as close to zero as possible. It is particularly important for the clock on the output side to be as stable and free of jitter as possible. For example, the clock on the output side should be influenced as little as possible by fluctuations in the supply voltage and its current delay time setting shall be independent of the drive of the delay unit.